1. Field of the Invention
The present invention relates to an overlay mark for measuring and correcting alignment errors of patterns. More particularly, the present invention relates to an overlay mark including a hole array and a linear trench to accurately measure alignment errors of patterns.
2. Description of the Related Art
Integrated circuit devices including minute patterns are generally formed by repeatedly performing unit processes such as a deposition process and a photolithography process. In the photolithography process, after a photoresist film is coated on a layer to be patterned, which is positioned on semiconductor substrate, the photoresist film is exposed and developed to form a photoresist pattern on the layer to be patterned. The layer is etched using the photoresist pattern as an etching mask to thereby form a desired pattern on the semiconductor substrate. When upper and lower patterns of an integrated circuit device are formed by the photolithography process, the upper patterns should be exactly aligned with regard to the lower patterns.
Precise alignments between the upper and lower patterns may be generally achieved through a reticle alignment and a wafer alignment performed in an exposure section of a photolithography apparatus. The alignments of the patterns are corrected in accordance with overlay correction data obtained by an overlay measuring process carried out in the photolithography apparatus. The overlay correction data are obtained by measuring a contrast of light detected from the overlay mark. The alignment errors of the patterns are measured using the overlay mark formed on a scribe line (scribe lane) of a semiconductor substrate, the scribe line dividing the semiconductor substrate into a plurality of dies.
However, alignment errors among patterns formed at predetermined portion of a semiconductor substrate may not be precisely measured using a conventional mark because the overlay mark has a shape and a size substantially different from those of the patterns positioned on the semiconductor substrate as integrated circuit devices have been highly integrated.
FIG. 1 is a plan view illustrating a conventional wafer.
Referring to FIG. 1, a conventional wafer 10 is divided into a plurality of dies 30 by a scribe line 20. Each of the dies 30 corresponds to a portion of the wafer where an integrated circuit device is formed. An overlay mark is formed on the scribe line 20 for aligning patterns of the integrated circuit device.
FIG. 2 is a cross-sectional view illustrating a conventional overlay mark, and FIG. 3 is an electron microscopic photograph illustrating a contrast of light detected from the conventional overlay mark.
Referring to FIG. 2, after a first layer 50 is formed on a semiconductor substrate 40, a first overlay mark 70 is formed on a scribe line B of the semiconductor substrate 40 and also a hole array 60 is formed at a predetermined portion A of the semiconductor substrate 40 where an integrated circuit device is formed. Because a contact size C of the hole array 60 is smaller than a size D of the first overlay mark 70, impurities 80 may be formed on the first overlay mark 70 due to over-etch of the first overlay mark 70 as shown in FIG. 3 when the hole array 60 and the first overlay mark 70 are simultaneously formed by a dry etching process. The impurities 80 are caused by etched by-products of the first layer 50 and a photoresist pattern. That is, the etched by-products are attached on and/or to the first overlay mark 70 to form the impurities 80.
FIG. 4 is a graph schematically illustrating the contrast of light detected from the conventional overlay mark using an overlay measurement apparatus.
Referring to FIGS. 3 and 4, the impurities 802 formed on the overlay mark 70 degrade a contrast of light 90 detected from the overlay mark 70 using an overlay measurement apparatus. Particularly, the impurities 80 cause an abnormal region E in the contrast of light 90 so that the contrast of light 90 may not be exactly detected from the overlay mark 70. Hence, alignment errors among patterns formed on a semiconductor may not be precisely measured using the contrast of the light 90 detected from the overlay mark 70.
FIGS. 5A and 5B are cross-sectional views illustrating a method of forming conventional overlay marks.
Referring to FIGS. 5A and 5B, a first overlay mark 75 and a second overlay mark 115 are formed on a semiconductor substrate 45. After a first layer 55 is formed on the semiconductor substrate 45, the first layer 55 is etched to form the first overlay mark 75 on the semiconductor substrate 45. The first overlay mark 75 has a rectangular shape (see FIG. 5A) or a rectangular band shape (see FIG. 5B). The second overlay mark 115 is formed over the first overlay mark 75, and a second layer 105 is interposed between the second overlay mark 115 and the first overlay mark 75. The second overlay mark 115 has a rectangular shape smaller than the first overlay mark 75.
FIGS. 6A and 6B are plan views illustrating a method of measuring alignment errors using the conventional overlay marks. FIGS. 6A and 6B show the first and second overlay marks 75 and 115 in FIGS. 5A and 5B, respectively.
Referring to FIGS. 6A and 6B, the semiconductor substrate 45 including the first and second overlay marks 75 and 115 is loaded into an overlay measurement apparatus. A horizontal distance dx and a vertical distance dy between the first and second overlay marks 75 and 115 are measured so as to detect alignment errors among patterns formed at a predetermined portion of the semiconductor substrate 45.
Considering the above-mentioned problem, Korean Laid Open Patent Publication No. 2001-5118 discloses an overlay mark including a plurality of minute patterns to properly measure alignment errors of patterns formed on a semiconductor substrate. Here, the minute patterns have sizes of about 0.25 μm to about 0.30 μm. However, when the minute patterns of the overlay mark include grooves of about 0.25 μm to about 0.30 μm, a contrast of light detected from the overlay mark may not be accurately measured because the overlay mark does not have a desired width. Additionally, the contrast of light detected from the overlay mark may not be exactly detected at a desired position when the minute patterns of the overlay mark include lines and spaces of about 0.25 μm to about 0.30 μm. Furthermore, the contrast of light detected from the overlay mark may be degraded when the minute patterns of the overlay mark include contact holes of about 0.25 μm to about 0.30 μm.